Voltage regulators are fundamental functions in powering most analog or digital functions in electronic systems. Operating at low currents, low power supply voltages, and over extended temperatures are key objectives in portable electronics systems, including in system-on-chips (SOC), especially in medical or emerging wireless and battery-less applications such as power-on-a-chip (PoC), Internet-of-things (loT), or energy harvesting, to name a few.
In light of the potentially large markets for such emerging applications, unless solution costs are low, the markets may not realize their full potential reach. As such, low cost innovations in component designs are needed to enable such prospects of high volume markets to get off the ground and take off. In the last few decades, there has been a tremendous amount of annual manufacturing investment in semiconductors, some of which is sunk-cost. As a result, there is likely ample capacity in standard complementary metal-oxide-semiconductor (CMOS) manufacturing factories that may be readily and cheaply available for exploitation by new and promising high volume markets. The enablement of such new high volume markets would greatly benefit if their solutions require neither any custom devices nor any special processes, which could impose higher costs or risks on manufacturing yields. For design solutions in such emerging applications, to optimally exploit the existing digital CMOS capacity, manufacturing process node-portability should not be impeded. While the die-size of such solutions need to be kept small to keep the costs down, optimally no performance interference on the rest of the functions of the SOC should be imposed by innovative designs when serving such new applications requirements (low voltage and ultra-low current over maximal power supply and temperature spans).
A survey of alternative voltage regulator topologies is presented in Fayomi, C J B. et al (2010) “Sub 1 V CMOS bandgap reference design techniques: a survey”, AICSP 62:141-157, DOI 10.1007/s10470-009-9352-4 discusses many techniques and their trade-offs for low power references and which is hereby incorporated by reference. Some of the trade-offs which are discussed in Fayomi et al. are briefly summarized as follows. Using Bipolar CMOS (BiCMOS) processes or depletion mode CMOS transistors frees up some operational supply headroom but adds to fabrication complexity and cost. Also, utilizing process deviations such as threshold differentials between positive channel metal-oxide semiconductors (PMOS) and negative channel metal-oxide semiconductors (NMOS), multiple depletion mode transistors, and differential thresholds via channel length variations. Alternatively, using custom devices such as a dynamic threshold metal-oxide semiconductor transistor (DTMOST), bulk driven CMOS, or lateral positive negative positive transistors (PNPs) can provide some design flexibility in extending digital power supply voltage (VDD) and bandgap voltage (VBG) spans, but at a price. Such deviations impose additional manufacturing costs, require special device modeling, or may demand post production control monitoring for the entire SOC that contains the reference. There are other design techniques, such as switch capacitors, that can provide extra operational headroom without the need for process or device variations. Switching techniques can help make low-noise references with stable temperature coefficients (TC) but may add cost due to capacitor extra mask or large capacitors for low droop rates. Chopping bandgap topologies can also cause high transient current consumption or may interfere with other substrate-noise sensitive analog functions within the SOC. Moreover, switch capacitor topologies can increase latch up risk and may require on chip charge-pumps in sub-1V environments. Banking only on CMOS transistors in subthreshold (which emulate pseudo-bipolar junction transistor (BJT) like behavior) to generate a VBG helps with low-power and sub-1V objectives, but such designs generally exhibit wider VBG variations, and likely require extra trimming and testing cost in post production. Forward biasing PMOS or NMOS body-source terminals can help increase bandgap amplifier headroom, but requires proper modeling at different process nodes. Additionally, such a design approach generally entails increased parasitic current and leakage risk at elevated temperatures, which limits the reference high temperature operations. The majority of reference topologies that impose on the SOC by requiring special processes or rely on non-standard use of transistors have not made it to high-volume applications. This is not just because of their added manufacturing cost, special device characterization, or special device modeling requirements. As noted earlier, variations on process, and deviation on devices for one function of an SOC (such as a reference) increases costs and manufacturing risk on the entire SOC and handicaps the SOC's process node portability, which ties the manufacturer's hands.